Process of forming an electronic device including depositing a conductive layer over a seed layer

ABSTRACT

A process of forming an electronic device can include placing a seed layer into an electroplating solution within an electroplating tool. The electroplating tool can include a first electrode and a second electrode, wherein the first electrode is electrically connected to the seed layer. The process can also include depositing a first portion of a conductive layer using a first signal of a first type (e.g., direct current) between the first electrode and a second electrode, and depositing a second portion of the conductive layer over the first portion of the conductive layer, using a second signal of a second type (e.g., alternating current) between the first electrode and the second electrode of the electroplating tool.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to processes of electroplating conductivelayers and more particularly to processes of electroplating conductivelayers using an electroplating tool.

2. Description of the Related Art

Electronic devices can include conductive layers that are deposited byelectroplating. One or more compounds can be added to an electroplatingsolution to affect the electroplating of a conductive layer over apatterned layer and within openings in the patterned layer. For example,a suppressor can be used to the reduce local electroplating rate alongthe upper corners of the openings, an accelerator can be added toincrease the local electroplating rate within the openings, and aleveler can be added to reduce the local electroplating rate along arelatively flat, exposed surface. When all three compounds are used,electroplating can be performed using direct current during all of theelectroplating.

A leveler is optional and may not be used. When a leveler is not used inthe electroplating solution, an alternating current is typically used.The process without the leveler has problems that are better understoodwith respect to the illustrations in FIGS. 1 and 2. FIG. 1 includes anillustration of a substrate 12 that includes openings 15 and 16, and aseed layer 14 that lies along the surface of the substrate 12 and withinthe openings 15 and 16. A barrier layer can be used and would liebetween the substrate 12 and the seed layer 14, but the barrier layer isnot illustrated to simplify understanding. The seed layer 14 lies alongthe upper exposed regions 112 of the substrate, the corners of theopenings 18, the sides of the openings 114, and the bottoms 110 of theopenings.

FIG. 2 includes an illustration after electroplating a conductive layer22 over the seed layer 12. One or more problems may occur duringelectroplating. For example, the accelerator can increase the depositionrate along the bottoms of the openings 110 relative to another location,such as the corners 18 of openings 15 and 16. As the opening 15 fills,the accelerator can remain active and continue to enhance the depositionrate through substantially the entire electroplating process. After theopening 15 has been filled, the accelerator can continue to affect thedeposition rate above the opening, and a mound 24 can be formed asillustrated near the left-hand side in FIG. 2.

A pulse reverse waveform can be used to help control the moundingwithout the complexity of adding and controlling the leveler to theelectroplating solution. However, when the current flow is reversed, aportion of the electroplated layer is removed. Again referring to FIG.1, the seed layer 14 has a relatively thinner portion along thesidewalls 114, where the resistance of the conductive layer 14 may behigher than another location where the seed layer 114 is relativelythicker. Such differences in resistance can shift the electroplating anddeplating rates differently at different locations along the seed layer14, and thus contribute to void formation when a pulse reverse waveformis used. Referring to the opening 16 to the right-hand side of FIG. 2, avoid 26 has been formed within the opening 16 during electroplating.After the electroplating, a workpiece may have mounds, voids, or acombination of mounds and voids.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerousfeatures and advantages made apparent to those skilled in the art byreferencing the accompanying drawings.

FIG. 1 includes an illustration of a cross-sectional view of a workpieceincluding a substrate, openings in the substrate, and a seed layer overthe substrate. (Prior art)

FIG. 2 includes an illustration of a cross section of the workpiece ofFIG. 1 after electroplating a conductive layer within the openings.(Prior art)

FIG. 3 includes an illustration of a cross-sectional view of a workpieceafter forming an opening in an insulating layer overlying a substrate toexpose a conductive portion of the substrate.

FIG. 4 includes an illustration of a cross-sectional view of theworkpiece of FIG. 3 after forming a barrier layer and a seed layer.

FIG. 5 includes an illustration of a schematic diagram of the workpieceof FIG. 4 within an electroplating tool.

FIG. 6 includes an illustration of a circuit within a controller of theelectroplating tool of FIG. 5.

FIG. 7 includes an illustration of a cross sectional view of theworkpiece of FIG. 5 when forming a first portion of a conductive layerover the seed layer.

FIG. 8 includes an illustration of a cross sectional view of theworkpiece of FIG. 7 when forming a second portion of the conductivelayer.

FIG. 9 includes an illustration of a cross sectional view of theworkpiece of FIG. 8 after removing the workpiece, including theconductive layer, from the electroplating tool.

FIG. 10 includes an illustration of a cross sectional view of theworkpiece of FIG. 9 after removing portions of the barrier, seed, andconductive layers.

FIG. 11 includes an illustration of a cross sectional view of a systemincluding an electronic device formed by a process described herein.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help to improveunderstanding of embodiments of the invention.

DETAILED DESCRIPTION

A process of forming an electronic device can include placing a seedlayer overlying a substrate into an electroplating solution within anelectroplating tool. A first electrode of the electroplating tool can beelectrically connected to the seed layer, and a second electrode of theelectroplating tool is disposed within the electroplating solution. Theprocess can include depositing a first portion of a conductive layerover the seed layer, wherein depositing the first portion is performedusing a first signal of a first type (e.g., direct current or DC)between the first electrode and a second electrode. The process canfurther include depositing a second portion of the conductive layer overthe first portion of the conductive layer, wherein depositing the secondportion is performed using a second signal of a second type (e.g.,alternating current or AC) between the first electrode and the secondelectrode of the electroplating tool.

In an exemplary, non-limiting embodiment, initial electroplating of theconductive layer can be performed using a DC signal, and subsequentelectroplating of the conductive layer can be performed using an ACsignal. The electroplating solution does not require a leveler as usedin conventional method where a DC signal is used during the entireelectroplating process. Therefore, costs and the technical complexity ofhaving an extra additive (e.g., the leveler) can be omitted. Also, byusing a DC signal during the initial electroplating, erosion of the seedlayer within the openings during the initial electroplating, which mayoccur with a reverse bias pulse of an AC signal, can be reduced oreliminated. Thus, in this particular embodiment, the mounding, voidformation, or both issues can be significantly reduced or potentiallyeliminated.

Attention is now directed to particular embodiments of forming anelectronic device, as illustrated in FIGS. 3 to 10. FIG. 3 includes anillustration of a cross-sectional view of a workpiece that includes apartially formed electronic device. The workpiece includes a substrate30 that can include a monocrystalline semiconductor wafer, asemiconductor-on-insulator wafer, a flat panel display (e.g., a siliconlayer over a glass electroplate), or other substrate conventionally usedto form electronic devices. An electronic component 314 lies within thesubstrate 30, over the substrate 30, or both. In a particularembodiment, the electronic component 314 can be a transistor, a diode, acapacitor, a resistor, or an inductor. As illustrated in FIG. 3, theelectronic component 314 includes a transistor structure. The workpiececan include many other electronic components that may be substantiallythe same or different from the electronic component 314.

An insulating layer 32 overlies the substrate 30 and the electroniccomponent 314. The insulating layer 32 can include an insulatingmaterial, such as an oxide, a nitride, an oxynitride, or a combinationthereof. The insulating layer 32 can include a single insulating film ora plurality of insulating films. The thickness of the insulating layer32 needs to be sufficient to provide electrical insulation betweenconductors at different elevations. Although the insulating layer 32does not have a theoretical upper limit on its thickness, otherconsiderations may limit the thickness of the insulating layer 34 from apractical standpoint (e.g., ability to form reproducibly openings to anunderlying conductor, equipment throughput, etc.). In one embodiment,the insulating layer 32 has thickness no greater then 5000 nm, nogreater than 2000 nm, or no greater than 900 nm, and in anotherembodiment, the insulating layer 32 has a thickness at least 110 nm, atleast 300 nm, or at least 700 μm. In still another embodiment, theinsulating layer 32 can be thicker or thinner than those thicknesses.

A conductive plug 34 lies within an opening within the insulating layer32. The conductive plug 34 is electrically connected to the electroniccomponent 314. The conductive plug 34 can include doped silicon,tungsten, another suitable conductive material, or any combinationthereof. The conductive plug 34 can include a glue layer, a barrierlayer, or any combination thereof before forming a fill material, suchas tungsten or the like.

An insulating layer 36 overlies the insulating layer 32. The insulatinglayer 32 can include an insulating material, such as an oxide, anitride, an oxynitride, or a combination thereof. The insulating layer36 can include a single insulating film or a plurality of insulatingfilms. As compared to the insulating layer 32, insulating layer 36 canhave the same or different composition, the same or different number offilms, and the same or different thickness.

An opening 38 is formed through the insulating layer 36 to expose theconductive plug 34. The width of the opening 38 is sufficiently wide toallow for the proper formation of a subsequently-formed conductor withinthe opening 38, but not so wide as to form a contact to a differentunderlying conductor to which a subsequently-formed conductor is not tomake electrical contact. The opening 38 has a width 310, which in oneembodiment is less than 900 nm, less than 300 nm, or less than 130 nm.The depth of the opening 38 is substantially the same as the thicknessof the insulating layer 32 near the opening 32. An aspect ratio is theratio of the depth of the opening 38 to the width of the opening 38 canbe 1:2, 1:1, 2:1, 5:1, 9:1, a higher ratio, or any value between thoselisted.

As used within this specification, length, width, and depth refer todifferent dimensions of feature. The length and width are seen from atop view of the feature, wherein the width is the same size or smallerthan the length, and depth is seen from a cross-sectional view of thefeature.

The workpiece with the component 314, insulating layers 32 and 36,conductive plug 34, and opening 38 are formed using conventional orproprietary techniques. Such techniques can include film growth, filmdeposition, etching, polishing, ion implantation, silicide reaction, orany combination thereof.

FIG. 4 includes an illustration of a cross-sectional view of theworkpiece 40 after forming a barrier layer 42 and a seed layer 44 overthe insulating layer 36 and within the opening 38. The barrier layer 42is formed over the insulating layer 36 and within the opening 38. Thebarrier layer 42 has a composition and thickness sufficient to keep amaterial from a subsequently-formed conductor from migrating into theinsulating layer 32, 36, or both. The barrier layer 42 can include anitrogen-containing material, such as a metal nitride, a metalsemiconductor nitride, or a combination thereof. For example, thebarrier layer can include TiN, Ti/TiN, TaN, Ta/TaN, WN, TaSiN, anothersuitable conductive nitrogen-containing material, or any combinationthereof. The barrier layer 42 can include a single film or more than onefilm. In one embodiment, the barrier layer 42 can include an adhesionfilm in addition to the nitrogen-containing film. The adhesion film liesbetween the insulating layer 36 and a nitrogen-containing film to reducethe likelihood that the nitrogen-containing film will delaminate fromthe insulating layer 36. In one embodiment, the barrier layer 42 has athickness no greater than 90 nm, no greater than 50 nm, or no greaterthan 30 nm, and in another embodiment, the barrier layer 42 has athickness at least 2 nm, at least 11 nm, or at least 20 nm. In stillanother embodiment, the barrier layer 42 can be thicker or thinner thanthose thicknesses. The barrier layer 42 can be formed by a conventionalor proprietary technique. In one embodiment, the barrier layer 42 can beformed by using a physical vapor deposition, such as sputtering.

A seed layer 44 is deposited over the barrier layer 42. The seed layer44 includes a conductive layer that promotes electroplating onto theworkpiece 40. The seed layer 44 typically includes the same materialthat will be subsequently electroplated. For example, if copper is to beelectroplated, the seed layer 44 can include copper. In anotherembodiment, the seed layer 44 can have a composition dissimilar to thematerial that will subsequently be electroplated. The thickness of theseed layer 44 is sufficient to cover all surfaces of the barrier layer42. In one embodiment, the seed layer 44 has a thickness no greater than90 nm, no greater than 50 nm, or no greater than 30 nm, and in anotherembodiment, the seed layer 44 has a thickness at least 2 nm, at least 11nm, or at least 20 nm. In still another embodiment, the seed layer 44can be thicker or thinner than those thicknesses. The seed layer 44 canbe formed by a conventional or proprietary technique. In one embodiment,the seed layer 44 can be formed by using a physical vapor deposition,such as sputtering.

In one embodiment, the barrier layer 42, the seed layer 44, or both maybe locally thinner along the side of the opening 38 than along surfaceof the insulating layer 32. Further, the thickness along the side of theopening 38 can decrease as a function of the distance from the top ofthe opening 38.

The barrier layer 42 and the seed layer 44 have a combined thickness 46that only partly, and not completely, fills the opening 38. In oneembodiment, the combined thickness 46 has a thickness no greater than 90nm, no greater than 50 nm, or no greater than 30 nm, and in anotherembodiment, the combined thickness 46 has a thickness at least 4 nm, atleast 11 nm, or at least 20 nm. In still another embodiment, thecombined thickness 46 can be thicker or thinner than those thicknesses.

In a further embodiment, the width 310 is no greater than 20 times thecombined thickness 46, no greater than 15 times the combined thickness46, or no greater than 9 times the combined thickness 46, and in still afurther embodiment, the width 310 is at least 3 times the combinedthickness 46, at least 5 times the combined thickness 46, or at least 7times the combined thickness 46. In still another embodiment, the width310 can be more times or less times the combined thickness 46. Theresulting workpiece 40 is ready for electroplating.

FIG. 5 includes an illustration of a schematic diagram of the workpiece40 within an electroplating tool 50. The electroplating tool 50 and itsrelationship with the workpiece 40 during electroplating are describedbefore addressing the details during the entry portion of theelectroplating process (i.e., when the workpiece 40 initially comes incontact with the electroplating solution 59).

The electroplating tool 50 includes a chamber 51 with an outlet port502. The electroplating tool 50 further includes a cup 52 that has aninlet port 512 for receiving an electroplating fluid. An anode (one ofthe electrodes of the electroplating tool 50) lies between the cup 52and workpiece 40. The anode includes a material that is to beelectroplated onto the workpiece. The anode can include an elementalmetal, such as copper, nickel, a noble metal (gold, silver, platinum,palladium, osmium, or iridium), or another suitable metal. In theembodiment as illustrated, the electroplating tool 50 includes threeanodes 541, 542, and 543. The anode 543 can be generally circular, andanodes 541 and 542 can be annular rings surrounding the anode 543. Eachof the anodes 541, 542, and 543 are coupled to a controller 58 that cancontrol the anodes 541, 542, and 543 independently of one another toallow for more uniform electroplating across the surface of theworkpiece 40. In another embodiment, more or fewer anodes can be used.

The electroplating tool further includes a head 55 that has a turntable551 and clamp ring 552. The clamp ring 552 is the cathode for theelectroplating tool 50 and is electrically coupled to the controller 58.The clamp ring 552 can include a conductive material that is dissimilarto the material that is to be electroplated onto the workpiece 40, suchthat material that electroplates onto the clamp ring 552 may besubsequently removed selective to the material that makes up the clampring 552. The workpiece 40 is mounted to the head 52 so that the seedlayer 44 (not illustrated in FIG. 5) is in contact with the clamp ring551. In other words, the workpiece 40 will be oriented such that theseed layer 44 is exposed to the electroplating solution 59 (faces theanodes 541, 542, and 543). In the operation of the electroplating tool50, the electroplating solution 59 enters the cup 52 through the inletport 512, flows by the anodes 541, 542, and 543, at which point ionsfrom the anodes 541, 542, and 543 are dissolved into the electroplatingsolution 59. The electroplating solution 59 eventually flows over thesides of the cup 52, down between the walls of the cup 52 and thechamber 51, and through the outlet port 502.

The composition of the electroplating solution 59 can depend on thematerial that is to be electroplated onto the workpiece 40. When copperis to be electroplated, the electroplating solution 59 can includecopper, copper sulfate (Cu₂SO₄), sulfuric acid (H₂SO₄), chloride ions,such as those from HCl, and water. Other chemicals are used if amaterial other than copper is to be electroplated. Skilled artisans willbe able to determine the basic chemistry for the material to beelectroplated.

The electroplating solution 59 can also include organic additives. Inone embodiment, the electroplating solution 59 includes an acceleratorand a suppressor. The accelerator helps to accelerate electroplatingnear the bottom of the opening 38 (see FIG. 4). The suppressor helps tosuppress electroplating near the upper corner of the opening 38. Theaccelerator can include a disulfide, and the suppressor can include apolymeric diol (e.g., polyethylene glycol or the like). After readingthis specification, another conventional or proprietary accelerator orsuppressor can be used in place of or in addition to the accelerator orsuppressor listed. In one embodiment, no leveler (e.g., an amine) isused in the electroplating solution 59. In another embodiment, more,fewer, or different additives can be used.

FIG. 6 includes a control circuit 60 within the controller 58. Thecontrol circuit can control the anode 541, 542, 543, or any combinationthereof. The control circuit includes switches 62 that can be configuredto allow current to flow through the upper conduction path or the lowerconduction path. The switches 62 can include a transistor, amultiplexer, a demultiplexer, a relay, a mechanical switch, anothersuitable switch, or the like. The switches 62 can be controlled manuallyor by suitable hardware, firmware, or software within the controller 58.

The upper conduction path includes a DC signal source 64 and a timingcircuit 66. The upper conduction path is used during entry and otherinitial electroplating. The timing circuit 66 can be used to reduce asudden surge in current when the workpiece 40 initially contacts theelectroplating solution 59, as will be described in more detail below.The timing circuit 66 can include a resistive component, a capacitivecomponent, an inductive component, or the like. If the timing circuit 66includes the capacitive component, the timing circuit 66 may include adischarge circuit to discharge the capacitive element before a differentworkpiece is electroplated. In another embodiment, the timing circuit 66may not be used.

The lower conduction path includes an AC signal source 68. The lowerconduction path is used during most of the electroplating.

Attention is now directed to details regarding the electroplatingprocess. Before the workpiece 40 contacts the electroplating solution59, the workpiece 40 is oriented to an angle different from a planedefined by the lip of the cup 52 and is rotated to reduce the likelihoodthat a bubble with form within the opening 38 of the workpiece 40). Inone embodiment, the angle (as measured from a horizontal plane as seenin FIG. 5) is no greater than 4 degrees or at no greater than 2.9degrees, and in another embodiment the angle is at least 1.1 degrees orat least 2.2 degrees.

The rotational speed can be high enough to reduce the likelihood ofbubble formation, but not so high as to cause splashing or otherturbulent or eddy effects. In one embodiment, the rotational speed is nogreater than 150 revolutions per minute (“rpm”), or no greater than 90rpm, and in another embodiment, the rotational speed is at least 50 rpmor at least 60 rpm.

The vertical entry speed can be as high as reasonable possible withoutcausing splashing, eddy or other turbulent effects. In one embodiment,the vertical entry speed is at no greater than 50 mm/s or no greaterthan 25 mm/s, and in another embodiment, the vertical entry speed is atleast 1 mm/s or at least 5 mm/s.

The workpiece 40 contacts the electroplating solution 49 when theelectroplating occurs. In one embodiment, the workpiece 40 is adjustedso that angle is approximately 0 degrees during most of theelectroplating. The workpiece 40 is typically submerged within theelectroplating solution 49. The workpiece 40 does not contact the anodes541, 542, and 543 during electroplating, and thus the workpiece 40 isspaced apart from the anodes 541, 542, and 543. If the workpiece 40 issubmerged too far, material may start to plate the backside of theworkpiece 40, which is undesired. In a particular embodiment, theworkpiece 40 can be submerged such that it is approximately 7 mm toapproximately 9 mm below a meniscus of the electroplating solution 49(near the top of the cup 52).

In a particular, non-limiting embodiment, the angle can be approximately2.6 degrees, the rotational speed can be approximately 75 rpm, thevertical entry speed can be approximately 15 mm/s, and the workpiece 40is submerged approximately 8 mm below the meniscus of the platingsolution. After reading this specification, skilled artisans will beable to determine particular entry parameters that meet their needs ordesires.

Electroplating is performed during two different portions that usedifferent types of signals. In one embodiment, the first portion isperformed using a DC signal, and the second portion is performed usingan AC signal. The first portion is schematically depicted in FIG. 7 toform a lower portion 72 of a conductive layer, and the second portion isschematically depicted in FIG. 8 to form an upper portion 82 of theconductive layer. The combination of anodes 541, 542, and 543 aredepicted an electrode 70, and the upper conduction path (in FIG. 6) isdepicted as a battery 74, and the lower conduction path (in FIG. 6) isdepicted as an alternator 84 to simplify understanding, even though theactual implementation may be more complicated.

Referring to FIGS. 5 and 6, the controller 58 activates the switches 62so that the upper conduction path in the control circuit 60 is active.The first portion of the electroplating includes an initial section anda primary section. The primary section is current controlled, and theinitial section is to transition as quick as reasonably possible to theprimary section. The initial section is to allow a transition to thecurrent control portion and to limit the voltage and current flowingbetween the anodes 541, 542, and 543 and the clamp ring 552. In oneembodiment, the voltage difference between the clamp ring 552 and eachof the anodes 541, 542, and 543 is no greater than 4 V or no greaterthan 3V, and in another embodiment is at least 0.5V or at least 1 V. Theinitial section lasts for no greater than 2 seconds. The DC signalsource 64, the timing circuit 66, or both can be used to control thevoltage, time, or both during the initial section. In a particularembodiment, the control circuit 60 can include a resistive element, acapacitive element, an inductive element, or any combination thereforeto substantially reduce the likelihood of a significant electrostaticshock when the workpiece 40 contacts the electroplating solution 59. Ina particular embodiment, an inductor-capacitor (“LC”) circuit can beused to allow the current flowing between the clamp ring 522 and anyanode or all of the anodes 541, 542, and 543 to increase current in acontrolled manner during the initial section.

During the primary section, the electroplating is current controlled.The voltage is allowed to vary during the primary section. Lower andupper theoretical limits for the current flux (current per area of thesubstrate, from a top view) are unknown. Practical limitations, such asthe current limit of the electroplating tool, may affect the currentused. In one embodiment, the current per unit area is no greater than 20mA/cm² or no greater than 15 mA/cm², and in another embodiment, thecurrent per unit area is at least 2 mA/cm² or at least 4 mA/cm². As thecurrent decreases, the time period for the primary section may belonger, and as the current increases, the time period for the primarysection may be shorter.

In an alternative embodiment, charge per unit area (product of currentper unit area times the time period of the primary section, initialsection, or both) may be monitored. In one embodiment, the charge perunit area is no greater than 0.09 coulombs/cm² or less than 0.07coulombs/cm², and in another embodiment, the charge per unit area is atleast 0.03 coulombs/cm² or at least 0.04 coulombs/cm².

In a particular, non-limiting embodiment, the initial section can beperformed with a voltage difference between the clamp ring 552 and eachof the anodes 541, 542, and 542 is approximately 2 volts for a timeperiod of no greater than 2 seconds, and the primary section isperformed at a current per unit area of approximately 10 mA/cm² and acharge per unit area of approximately 0.05 coulombs/cm². After readingthis specification, skilled artisans will appreciate that these or otherparameters may be used to meet the needs or desires for a particularapplication. At the end of the first portion of the electroplatingoperation, a lower portion 72 of the conductive layer has been formed,as illustrated in FIG. 7. The lower portion 72 of the conductive layerdoes not completely fill the opening 38. In one embodiment, the lowerportion 72 has a thickness of no greater than 150 nm or no greater than80 nm, and in another embodiment, the lower portion has a thickness ofat least 20 nm or at least 30 nm.

The second portion of the electroplating is performed to form the upperportion 82 of the conductive layer, as illustrated in FIG. 8. The upperportion 82 fills the remainder of the opening 38. The second portion canbe performed using an AC signal. Referring briefly to FIG. 6, theswitches 62 in the control circuit 60 can be changed to deactivate theupper conduction path and activate the lower conduction path. Thus, theAC signal source 68 can now be active and produce the AC signal. The ACsignal can be in the form of pulses, a sinusoidal waveform, anothersuitable polarity changing function, or any combination thereof Thesecond portion can be current controlled. In one particular embodiment,forward biased pulses and reversed bias pulses can be used. Duringforward biasing, each of the anodes 541, 542, and 543 is at a higherpotential than the clamped ring 552, and thus, copper is electroplatedonto the workpiece 40. During reverse biasing, each of the anodes 541,542, and 543 is at a lower potential than the clamp ring 552, and thus,copper is deplated (removed) from the workpiece 40. More copper iselectroplated during forward biasing as compared to the amount of copperremoved during reverse biasing. Thus, the absolute value of thecumulative charge during forward biasing is greater than the absolutevalue of the cumulative charge during reverse biasing. In this manner,the net effect of one cycle is to thicken the conductive layer.

During formation of the upper portion 82 of the conductive layer, thethickness of the upper portion 82 is a function of the charge duringforward biasing minus the charge during reverse biasing or

t _(UP) =f(Q _(f) −Q _(r)),

wherein t_(UP) is the thickness of the upper portion 82, Q_(f) is thecharge during forward biasing (product of current and time), and Q_(r)is the charge during reverse biasing (product of current and time).

If the current per unit area during forward biasing is too high, theopening 38 may not fill properly (e.g., from the bottom of the opening38). In one embodiment, the current per unit area during forward biasingis no greater than 50 mA/cm2 or no greater than 40 mA/cm2, and inanother embodiment, the current per unit area is at least 1.5 mA/cm2 orat least 11 mA/cm2. The time period for each pulse during forwardbiasing may be no greater than 900 ms or no greater than 200 ms, and inanother embodiment, the time period of at least 30 ms or at least 50 ms.In a particular embodiment, a ratio of the forward bias current to thereverse bias current is in a range of approximately 1.3 to 1.7. In oneembodiment, the current per unit area during reverse biasing is nogreater than 33 mA/cm2 or no greater than 20 mA/cm2, and in anotherembodiment, the current per unit area is at least 1.1 mA/cm2 or at least11 mA/cm2. The time period for each pulse during forward biasing may beno greater than 500 ms or no greater than 200 ms, and in anotherembodiment, the time period of at least 10 ms or at least 15 ms.

Between each of the forward bias pulses and the reverse bias pulses, nocurrent flows between the clamp ring 522 and each of the anodes 541,542, and 543, and is referred herein as an off pulse. No theoreticallimits on the off pulses are known; however, the material throughput canbe adversely affected if the off pulses are too long. In one embodiment,the time period for the off pulse in no greater than 500 ms or nogreater than 90 ms, and in another embodiment, the time period is atleast 0.5 ms or at least 2 ms.

FIG. 9 illustrates a cross-sectional view of the workpiece 40, includingthe lower portion 72 and the upper portion 82 after electroplating hasbeen completed. The exposed surface of the upper portion 82 may or maynot have a substantially planar surface.

FIG. 10 includes an illustration of a cross-sectional view of theworkpiece 40 after parts of the upper portion 82 and the lower portion72 of the conductive layer, the seed layer 44, and the barrier layer 42overlying the insulating layer 34 and lying outside the opening 36 havebeen removed. The removal can be performed by chemical-mechanicalpolishing, etching, or any combination thereof In one particularembodiment, the upper portion 82 and the lower portion 72 of theconductive layer and the seed layer 44 all principally include coppercan be removed by the same chemical-mechanical polishing operation. Thebarrier layer 42 can be removed using a different chemical-mechanicalpolishing operation (e.g., different polishing pad, different polishingslurry, different downforce pressure, etc.) or using plasma etching(e.g., reactive ion etching). The removal of the upper portion 82 andthe lower portion 72 of the conductive layer, the seed layer 44, and thebarrier layer 42 overlying the insulating layer 34 and lying outside theopening 36 can be performed using a conventional or proprietaryoperation, and such operation may or may not include endpoint detection.

Processing of the workpiece 40 can be continued to form a substantiallycompleted electronic device. In one embodiment (not illustrated),additional insulating and conductive layers can be formed and patternedto form one or more additional levels of interconnects. After the lastinterconnect level has been formed, an encapsulating layer is formed.The encapsulating layer can include an oxide, a nitride, an oxynitride,or a combination thereof. The encapsulating layer can include a singleinsulating film or a plurality of insulating films. The thickness anddeposition of the encapsulating layer can be conventional orproprietary.

FIG. 11 includes an illustration of a system 1 16. The system 116includes the electronic device 112 formed by the process describedherein. In one embodiment, the electronic device 112 can be anintegrated circuit that may include memory cells, such as nonvolatilememory cells, random access memory cells, other suitable memory cells,or any combination thereof. The electronic device 112 can be part of astandalone memory integrated circuit or may be part of a different typeof integrated circuit.

The system 116 also includes a processor 114 that is coupled to adisplay 118 and the electronic device 112. The processor 114 can includea central processing unit, a graphical processing unit, another suitableprocessing unit, or any combination thereof. The processor 114 may bepart of a microcontroller, a microprocessor, a digital signal processor,another suitable data processing integrated circuit or the like. Theprocessor 114 and the electronic device 112 can be separate integratedcircuits mounted on the same or different printed wiring boards. Inanother embodiment, the processor 114 and the electronic device 112 mayreside within the same integrated circuit. In one specific embodiment,the processor 114 can read data from the electronic device 112 andrender or otherwise provide information to be displayed on the display118 of the system 116.

Embodiments as described herein can be used to electroplate a materialby using a simpler electroplating chemistry without adverse consequencesthat can occur when using the simpler electroplating chemistry. Thesecond portion of the electroplating can be performed using an ACsignal, and therefore, a leveler, which is typically used withelectroplating using only a DC signal, is not required. Problems withthinning the seed layer 44, particularly along the sidewall of theopening 38 can be avoided because a first portion of the electroplatingis performed using a DC signal, rather than using only an AC signal whenelectroplating the entire conductive layer. Thus, the first portionusing the DC signal can deposit a significant portion of material alongthe sidewall, such that during the second portion, the AC signal mayremove a part of the lower portion of the conductive layer, but will notremove a significant part of the seed layer 44.

The processes herein can be used to form a conductive layer that doesnot form a mound over or a void within an opening. Thus, polishing maybe simplified, and reliability can be improved.

The embodiments can be implement using an existing electroplating tool,and therefore, does not require any capital investment. Additionally,the processes described herein can be implemented without anysignificant reduction in electroplating capacity. The processes may beimplemented by changes in software. Some of the values of parameters canbe scaled for different sizes of substrate.

Many different aspects and embodiments are possible. Some of thoseaspects and embodiments are described below. After reading thisspecification, skilled artisans will appreciate that those aspects andembodiments are only illustrative and do not limit the scope of thepresent invention.

In a first aspect, a process of forming an electronic device can includeplacing a seed layer overlying a substrate into an electroplatingsolution within an electroplating tool, wherein a first electrode of theelectroplating tool is electrically connected to the seed layer, and asecond electrode of the electroplating tool is in disposed within theelectroplating solution. The process can also include depositing a firstportion of a conductive layer over the seed layer, wherein depositingthe first portion is performed using a first signal of a first typebetween the first electrode and a second electrode. The process canfurther include depositing a second portion of the conductive layer overthe first portion of the conductive layer, wherein depositing the secondportion is performed using a second signal of a second type between thefirst electrode and the second electrode of the electroplating tool, andwherein the second signal type is different from the first signal type.

In one embodiment of the first aspect, the process further includesforming the seed layer over the substrate, wherein the substrateincludes an electronic component and an insulating layer over theelectronic component, and wherein the insulating layer includes anopening extending therethrough. The process still further includesforming the seed layer includes depositing the seed layer over theinsulating layer and within the opening, such that the seed layer iselectrically connected to the electronic component, and only a portionof the opening is filled with the seed layer. In a particularembodiment, the process further includes forming a barrier layer beforeforming the seed layer, wherein after forming the seed layer, a width ofthe opening in the insulating layer is no greater than approximately 20times the combined thickness of the barrier layer and the seed layer, asmeasured over the insulating layer.

In another embodiment of the first aspect, the first signal type isdirect current, and the second signal type is alternating current. In aparticular embodiment, during depositing the first portion of theconductive layer, the current flow is not greater than approximately 14milliamps per square centimeter of substrate area from a top view of thesubstrate. In still another embodiment placing the seed layer overlyingthe substrate into the electroplating solution includes lowering theseed layer and the substrate into the electroplating solution such thatthe substrate is a range of approximately 7 mm to approximately 9 mmbelow a meniscus of the electroplating solution. In yet anotherembodiment, the process further includes applying a potential differencebetween the first electrode and the second electrode before placing theseed layer into the electroplating solution, wherein the potentialdifference is not greater than approximately 4 volts.

In a further embodiment of the first aspect, depositing the firstportion of the conductive layer ends after not greater thanapproximately 0.07 coulombs per square centimeter of substrate area, asseen from a top view of the substrate, flows between the first electrodeand the second electrode. In still a further embodiment, theelectroplating solution includes a disulfide compound, a polyethyleneglycol compound, and substantially no amine compound. In yet a furtherembodiment, the second electrode includes a plurality of second anodes,and each anode of the plurality of second anodes is independentlycontrolled from each other.

In a second aspect, a process of forming electronic device can includeelectrically connecting a first electrode of an electroplating tool anda seed layer overlying a semiconductor substrate to each other, andapplying a potential difference as a direct current signal between thefirst electrode and a second electrode of the electroplating tool,wherein the second electrode is spaced apart from the first electrodeand the seed layer, is disposed within an electroplating solution of theelectroplating tool, and the electroplating solution includessubstantially no amine. The process can also include placing the seedlayer into an electroplating solution after applying the potentialdifference between the first electrode and the second electrode. Theprocess can further include depositing a first portion of a conductivelayer over the seed layer, wherein depositing the first portion endsafter not greater than approximately 0.07 coulombs per square centimeterof substrate area, from a top view of the substrate, flows from thefirst electrode to the second electrode. The process can still furtherinclude depositing a second portion of the conductive layer over thefirst portion of the conductive layer, wherein depositing the secondportion is performed using an alternating current signal between thefirst electrode and the second electrode.

In one embodiment of the second aspect, the process of claim 11, furtherincludes forming an insulating layer over the substrate, forming anopening in the insulating layer to expose a conductive structure,wherein the opening has an aspect ratio greater than one, and formingthe seed layer over the insulating layer and within the opening of theinsulating layer before electrically connecting the first electrode ofthe electroplating tool and the seed layer. In a particular embodiment,the process further includes forming a barrier layer over the conductivestructure before forming the seed layer. In another particularembodiment, the opening in the insulating layer has a width no greaterthan approximately 130 nm.

In still another embodiment of the second aspect, placing the seed layerin contact with the electroplating solution is performed such that theelectroplating solution includes a suppressor and an accelerator. In aparticular embodiment, the suppressor includes a polyethylene glycolcompound, and the accelerator includes a disulfide compound. In yetanother embodiment, applying the potential difference is performed suchthat the voltage difference of no greater than approximately 4 volts.

In a further embodiment of the second aspect, the process furtherincludes increasing a current flowing between the first electrode andthe second electrode during placing the seed layer into theelectroplating solution, during depositing a first portion of aconductive layer over the seed layer, or both. In still a furtherembodiment, the semiconductor substrate includes an electronic componentand, after depositing the first and the second portions of theconductive layer, the conductive layer is electrically coupled to theelectronic component. In yet a further embodiment, placing the seedlayer into an electroplating solution includes submerging thesemiconductor substrate into the electroplating solution, such that thesemiconductor substrate is approximately 7 mm to approximately 9 mmbelow a meniscus of the electroplating solution.

Note that not all of the activities described above in the generaldescription or the examples are required, that a portion of a specificactivity may not be required, and that one or more further activitiesmay be performed in addition to those described. Still further, theorder in which activities are listed are not necessarily the order inwhich they are performed.

In the foregoing specification, the concepts have been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the invention as set forth in theclaims below. Accordingly, the specification and figures are to beregarded in an illustrative rather than a restrictive sense, and allsuch modifications are intended to be included within the scope ofinvention.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any feature(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature of any or all the claims.

After reading the specification, skilled artisans will appreciated thatcertain features are, for clarity, described herein in the context ofseparate embodiments, may also be provided in combination in a singleembodiment. Conversely, various features that are, for brevity,described in the context of a single embodiment, may also be providedseparately or in any subcombination. Further, references to valuesstated in ranges include each and every value within that range.

1. A process of forming an electronic device comprising: placing a seedlayer overlying a substrate into an electroplating solution within anelectroplating tool; depositing a first portion of a conductive layerover the seed layer, wherein depositing the first portion is performedusing a first signal of a first type while the substrate is within theelectroplating tool; and depositing a second portion of the conductivelayer over the first portion of the conductive layer, wherein depositingthe second portion is performed using a second signal of a second typewhile the substrate is within the electroplating tool, and wherein thesecond signal type is different from the first signal type.
 2. Theprocess of claim 1, further comprising forming the seed layer over thesubstrate, wherein: the substrate includes an electronic component andan insulating layer over the electronic component, wherein theinsulating layer includes an opening extending therethrough; and formingthe seed layer comprises depositing the seed layer over the insulatinglayer and within the opening, such that the seed layer is electricallyconnected to the electronic component, and only a portion of the openingis filled with the seed layer.
 3. The process of claim 2, furthercomprising forming a barrier layer before forming the seed layer,wherein after forming the seed layer, a width of the opening in theinsulating layer is no greater than approximately 20 times the combinedthickness of the barrier layer and the seed layer, as measured over theinsulating layer.
 4. The process of claim 1, wherein the first signaltype is direct current, and the second signal type is alternatingcurrent.
 5. The process of claim 4, wherein during depositing the firstportion of the conductive layer, the current flow is not greater thanapproximately 14 milliamps per square centimeter of substrate area froma top view of the substrate.
 6. The process of claim 1, wherein placingthe seed layer overlying the substrate into the electroplating solutioncomprises lowering the seed layer and the substrate into theelectroplating solution such that the substrate is a range ofapproximately 7 mm to approximately 9 mm below a meniscus of theelectroplating solution.
 7. The process of claim 1, further comprising:electrically connecting to the seed layer to a first electrode of theelectroplating tool that is spaced apart from a second electrode of theelectroplating tool; and applying a potential difference between thefirst electrode and the second electrode before placing the seed layerinto the electroplating solution, wherein the potential difference isnot greater than approximately 4 volts.
 8. The process of claim 1,wherein: the process further comprises electrically connecting to theseed layer to a first electrode of the electroplating tool that isspaced apart from a second electrode of the electroplating tool; anddepositing the first portion of the conductive layer ends after notgreater than approximately 0.07 coulombs per square centimeter ofsubstrate area, as seen from a top view of the substrate, flows betweenthe first electrode and the second electrode.
 9. The process of claim 1,wherein the electroplating solution includes a disulfide compound, apolyethylene glycol compound, and substantially no amine compound. 10.The process of claim 1, further comprising electrically connecting tothe seed layer to a first electrode of the electroplating tool that isspaced apart from a second electrode of the electroplating tool, whereinthe second electrode includes a plurality of second anodes, and eachanode of the plurality of second anodes is independently controlled fromeach other.
 11. A process of forming electronic device comprising:electrically connecting a first electrode of an electroplating tool anda seed layer overlying a semiconductor substrate to each other; applyinga potential difference as a direct current signal between the firstelectrode and a second electrode of the electroplating tool, wherein thesecond electrode is spaced apart from the first electrode and the seedlayer, is disposed within an electroplating solution of theelectroplating tool, and the electroplating solution includessubstantially no amine; placing the seed layer into an electroplatingsolution after applying the potential difference between the firstelectrode and the second electrode; depositing a first portion of aconductive layer over the seed layer, wherein depositing the firstportion ends after not greater than approximately 0.07 coulombs persquare centimeter of substrate area, from a top view of the substrate,flows from the first electrode to the second electrode; and depositing asecond portion of the conductive layer over the first portion of theconductive layer, wherein depositing the second portion is performedusing an alternating current signal between the first electrode and thesecond electrode.
 12. The process of claim 11, further comprising:forming an insulating layer over the substrate; forming an opening inthe insulating layer to expose a conductive structure, wherein theopening has an aspect ratio greater than one; and forming the seed layerover the insulating layer and within the opening of the insulating layerbefore electrically connecting the first electrode of the electroplatingtool and the seed layer.
 13. The process of claim 12, further includingforming a barrier layer over the conductive structure before forming theseed layer.
 14. The process of claim 12, wherein the opening in theinsulating layer has a width no greater than approximately 130 nm. 15.The process of claim 11, wherein placing the seed layer in contact withthe electroplating solution is performed such that the electroplatingsolution includes a suppressor and an accelerator.
 16. The process ofclaim 15, wherein the suppressor includes a polyethylene glycolcompound, and the accelerator includes a disulfide compound.
 17. Theprocess of claim 11, wherein applying the potential difference isperformed such that the voltage difference of no greater thanapproximately 4 volts.
 18. The process of claim 11, further comprisingincreasing a current flowing between the first electrode and the secondelectrode during placing the seed layer into the electroplatingsolution, during depositing a first portion of a conductive layer overthe seed layer, or both.
 19. The process of claim 11, wherein thesemiconductor substrate includes an electronic component and, afterdepositing the first and the second portions of the conductive layer,the conductive layer is electrically coupled to the electroniccomponent.
 20. The process of claim 11, wherein placing the seed layerinto an electroplating solution comprises submerging the semiconductorsubstrate into the electroplating solution, such that the semiconductorsubstrate is approximately 7 mm to approximately 9 mm below a meniscusof the electroplating solution.